System on Chip implementation of wave-pipelined 2D DWT

This paper presents the design and implementation of hybrid wave-pipelined 2D DWT using lifting scheme. In this approach different lifting blocks are interconnected using pipelining and the individual blocks are implemented using WavePipelining (WP). For the purpose of comparison, non pipelined scheme as well as the scheme with pipelining within the blocks and between the blocks is implemented. For images of size 512×512, one level 2D DWT scheme is implemented on Xilinx based SOC Kits, using all the three schemes. From the implementation results, it is concluded that the hybrid WP is faster than non-pipelined and requires less area, less clock routing complexity and lower power than pipelined. The one level 2D DWT scheme is also implemented, in ASICs using pipelining. This is first of its kind. Key-Words: FPGA, SOC, ASIC, DWT, lifting.